1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device incorporating a data memory testing circuit.
2. Description of the Related Art
As the amount of data stored in a data memory increases, a clock frequency used to determine the data write and read frequencies rises, and the operating speed also rises accordingly. To test the operation of a large-capacity, high-speed data memory, a testing apparatus must have a high-speed testing function matching the operating speed of the data memory. That is, during testing, expected value data is compared with write data supplied to the data memory or compared with data to be tested read out from the data memory. A high-speed data line is required to supply this expected value data at high speed to the data memory or to externally supply the expected value data. A testing apparatus configured like this is expensive.
Also, when an inexpensive testing apparatus is to be used, the clock frequency may be lowered. Therefore, the test of a large-capacity data memory is time-consuming and unable to find inconvenience which appears only during a high-speed operation.
An example of the conventional semiconductor integrated circuit device testing methods is described in Jpn. Pat. Appln. KOKAI Publication No. 11-260095. However, this reference only describes a testing method which generates a decrement address instruction inside a circuit on the basis of an increment address instruction which is externally supplied to a RAM, and does not mention any means for solving the conventional problems as described above.